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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Master-Slave Flip-Flop
The MC10135 is a dual master-slave dc coupled J-K flip-flop. Asynchro- nous set (S) and reset (R) are provided. The set and reset inputs override the clock. A common clock is provided with separate J-K inputs. When the clock is static, the J-K inputs do not effect the output. The output states of the flip-flop change on the positive transition of the clock.
MC10135
L SUFFIX CERAMIC PACKAGE CASE 620-10 P SUFFIX PLASTIC PACKAGE CASE 648-08 FN SUFFIX PLCC CASE 775-02
PD fTog tpd tr, tf
= 280 mW typ/pkg (No Load) = 140 MHz typ = 3.0 ns typ = 2.5 ns typ (20%-80%)
LOGIC DIAGRAM
VCC1 Q1
J1 7 K1 6 R1 4 C9 S2 12 J2 10 K2 11 R2 13 Q2 Q2 15 14 Q1 Q1 2
DIP PIN ASSIGNMENT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q2 R2 S2 K2 J2 C
S1 5
Q1
3
R1 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 S1 K1 J1 VEE
R-S TRUTH TABLE
R L L H H S L H L H Qn+1 Qn H L N.D.
CLOCK J-K TRUTH TABLE*
J L H L H K L L H H Qn+1 Qn L H Qn
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6-11 of the Motorola MECL Data Book (DL122/D).
N.D. = Not Defined
* Output states change on positive transition of clock for J-K input condition present.
3/93
(c) Motorola, Inc. 1996
3-22
REV 5
MC10135
ELECTRICAL CHARACTERISTICS
Test Limits Pin Pi Under Test 8 6,7,9,10,11 4,5,12,13 4,5,6,7,9, 10,11,12,13 2 2 (3.) 3 3 (3.) 2 2 (4.) 3 3 (4.) 0.5 0.5 -1.060 -1.060 -1.890 -1.890 -1.080 -1.080 -1.655 -1.655 -0.890 -0.890 -1.675 -1.675 -30C Min Max 75 425 620 0.5 0.5 -0.960 -0.960 -1.850 -1.850 -0.980 -0.980 -1.630 -1.630 -0.810 -0.810 -1.650 -1.650 Min +25C Typ 54 Max 68 265 390 0.3 0.3 -0.890 -0.890 -1.825 -1.825 -0.910 -0.910 -1.595 -1.595 -0.700 -0.700 -1.615 -1.615 Min +85C Max 75 265 390 Unit mAdc Adc Adc Vdc Vdc Vdc Vdc ns t9+2+ t9+2- t2+, t3+ t2-, t3- 2 2 2, 3 2, 3 1.8 1.8 1.1 1.1 5.0 5.0 4.8 4.8 1.8 1.8 1.1 1.1 3.0 3.0 2.0 2.0 4.5 4.5 4.5 4.5 1.8 1.8 1.1 1.1 4.6 4.6 4.7 4.7 ns Propagation Delay t5+2+ t12+15+ t5+3- t12+14- 2 15 3 14 1.8 1.8 1.8 1.8 5.6 5.6 5.6 5.6 1.8 1.8 1.8 1.8 3.0 3.0 3.0 3.0 5.0 5.0 5.0 5.0 1.8 5.2 5.2 5.2 5.2 ns t4+2- t4+3- t13+15- t13+14+ tsetup thold 2 3 15 14 7 7 1.8 1.8 1.8 1.8 2.5 1.5 5.6 5.6 5.6 5.6 1.8 1.8 1.8 1.8 2.5 1.5 125 3.0 3.0 3.0 3.0 1.0 1.0 140 5.0 5.0 5.0 5.0 1.8 1.8 1.8 1.8 2.5 2.5 125 5.2 5.2 5.2 5.2 ns ns MHz
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH IinL
Output Voltage Output Voltage Threshold Voltage Threshold Voltage
Logic 1 Logic 0 Logic 1 Logic 0
VOH VOL VOHA VOLA
Switching Times (50 Load) Clock Input Propagation Delay Rise Time Fall Time Set Input (20 to 80%) (20 to 80%)
Reset Input Propagation Delay
Setup Time Hold Time
Toggle Frequency (Max) ftog 2 125 1. Individually test each input; apply VIHmax to pin under test. 2. Individually test each input; apply VILmin to pin under test.
3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax VILmin VIHAmax VILAmin
MECL Data DL122 -- Rev 6
3-23
MOTOROLA
MC10135
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 6,7,9,10,11 4,5,12,13 4,5,6,7,9, 10,11,12,13 2 2 (3.) 3 3 (3.) 2 2 (4.) 3 3 (4.) 5 6 5 6 5 6 5 6 Pulse In Propagation Delay Rise Time Fall Time Set Input Propagation Delay t5+2+ t12+15+ t5+3- t12+14- 2 15 3 14 5 12 5 12 2 15 3 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 (20 to 80%) (20 to 80%) t9+2+ t9+2- t2+, t3+ t2-, t3- 2 2 2, 3 2, 3 9 9 9 9 Pulse Out 2 2 2, 3 2, 3 Note 1. Note 1. Note 2. Note 2. VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH IinL
Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Clock Input
Logic 1 Logic 0 Logic 1 Logic 0 (50 Load)
VOH VOL VOHA VOLA
Reset Input Propagation Delay t4+2- t4+3- t13+15- t13+14+ tsetup thold 2 3 15 14 7 7 4 4 13 13 6, 9 6, 9 9 2 3 15 14 2 2 2 8 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
Setup Time Hold Time Toggle Frequency (Max)
ftog 2 1. Individually test each input; apply VIHmax to pin under test. 2. Individually test each input; apply VILmin to pin under test. 3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax VILmin VIHAmax
VILAmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MOTOROLA
3-24
MECL Data DL122 -- Rev 6
MC10135
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D Z
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
20
1
X V VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R
0.007 (0.180) M T L-M 0.007 (0.180) M T L-M
S
N N
S
S
S
H
0.007 (0.180) M T L-M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
MECL Data DL122 -- Rev 6
3-25
MOTOROLA
MC10135
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
9
-A-
16
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA 3-26
*MC10135/D*
MC10135/D MECL Data DL122 -- Rev 6

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